1. Field of the Disclosure
The present disclosure relates to polishing compositions, and methods for polishing semiconductor substrates using the same. More particularly, this disclosure relates to polishing compositions and methods for selectively polishing silicon nitride films over other dielectric films in semiconductor substrates containing multiple dielectric and metal films.
2. Description of the Related Art
The semiconductor industry is continually driven to improve chip performance by further miniaturization of devices by process and integration innovations. Chemical Mechanical Polishing/Planarization (CMP) is a powerful technology as it makes many complex integration schemes at the transistor level possible, thereby increasing chip density. Not surprisingly, there are a multitude of new CMP steps and requirements at the Front End of Line (FEOL) transistor fabrication step. These steps are new CMP requirements; quite different from the traditional shallow trench isolation (STI) and oxide polishing steps. These “exotic” FEOL CMP steps and processes started gaining attention (when compared to Back End of Line (BEOL) CMP) after the introduction of high-k metal gate technology at 45 nm and FinFET technology at 22 nm chip production by the Intel Corporation. Particularly, in many of these advanced integration schemes, silicon nitride (SiN) films are used as an Etch stop layer, capping material, and Hard Mask. In addition, SiN is also used as a diffusion or passivation layer, spacer material, and additional liner. In all such schemes, the SiN is used in combination with other dielectric films such as silicon oxide (e.g., TEOS) and poly-silicon. Thus, the chip manufacturing steps involving such integration schemes require selective polishing or removal of SiN films without removing the other dielectric material (such as TEOS). Therefore, for such kind of CMP polishing steps, slurries with very high and selective removal of SiN to silicon oxide films are required as most patterned wafers contain both the dielectric films at different density and feature size.
Other schemes, in which a composition that selectively polishes SiN over silicon oxide (e.g., TEOS) is required, are the “Reverse STI processes” and replacement of “Classic Etch Back processes.” In the language of the field, a SiN selective composition over silicon oxide implies a CMP composition that polishes SiN films at very high Material Removal Rates (MRRs) and simultaneously polishes silicon oxide at very low (and near to zero) MRRs thereby removing SiN selectively versus silicon oxide films. For example, a STI composition displays very high silicon oxide rates and very low SiN MRRs. Conversely, a “Reverse STI” composition displays very high SiN rates and very low silicon oxide MRRs, or, in other words, polishes SiN selectively versus silicon oxide films in pattern structures involving both the films.
The same properties are shown on blanket wafers which contain only an individual film—high SiN rates on blanket SiN wafers and low (to zero) oxide rates on blanket TEOS wafers. However, at times, the selectivity is higher on blanket wafers than observed on patterned wafers. In addition to Reverse STI processes, the SiN selective slurries are now being used in CMP processes that replace Etching processes in schemes involving removal of SiN by “Classic Etch Back processes.” In such schemes, it is desirable to utilize CMP rather than Etching methods because CMP delivers better defectivity and higher planarity on the substrate surface; to meet the ever increasing stringent requirements of semiconductor manufacturing.
FIG. 1 displays two applications, as examples, in which the Reverse STI CMP composition is used to polish off the SiN layer and then stop on the Silicon Oxide layer. After this Reverse STI CMP step, the semiconductor substrate is further processed.
The present disclosure provides stable compositions that show very high selectivities of SiN to silicon oxide by achieving nearly zero silicon oxide MRRs. The main body of the disclosure discusses the unique technologies that distinguish this disclosure from prior art.